Integrated circuit devices are tested after fabrication to ensure device performance according to functional specifications. Typically, an automatic electrical test system is programmed to provide an integrated circuit device with a simulated operating environment. Very-large-scale-integration (VLSI) devices require an automatic electrical test system capable of processing a large number of high speed input/output pins.
In a typical automatic electrical test system, timing parameters for a waveform are specified by a T1 marker and a T2 marker. The T1 marker and the T2 marker correspond to edges of the waveform in relation to a tester cycle. The T1 marker is specified by a T1 counter value and a T1 vernier value. A vernier is an auxiliary device for giving a piece of apparatus a higher adjustment accuracy. The T1 counter value and a T1 vernier value determine the T1 marker offset from the start of a tester cycle. The T2 marker is specified by a T2 counter value and a T2 vernier value. The T2 counter value and a T2 vernier value determine the T2 marker offset from the T1 marker or the start of the tester cycle.
In prior automatic electrical test systems, the tester cycles are typically generated by a central period generator. The central period generator is typically comprised of a base period generator and a period counter. The period counter is driven by a base period signal generated by the base period generator. The period counter is loaded with a tester period count and driven down to a terminal count, thereby generating a period start signal for a tester cycle. The central period generator distributes the period start signal and the base period signal to the marker generators for the output pins of the automatic electrical test system. The central period generator also distributes a period vernier value to the marker generators. The period vernier value is used to interpolate the period start signal in order to improve timing resolution.
In each marker generator, a T1 counter is loaded with the T1 counter value for the output pin. The T1 counter is driven by the base period signal received from the central period generator. The period start signal received from the central period generator causes the T1 counter to count down and generate a T1 terminal count signal.
Timing vernier circuits subdivide the base period signal in order to produce high resolution for the timing signals. The T1 terminal count signal is coupled to a T1 vernier circuit that interpolates the T1 terminal count signal according to the T1 vernier value for the output pin. The distributed period vernier value is used to modify the marker vernier values.
Past automatic electrical test systems that generate and distribute the period start signal and the period vernier value from a central period generator typically have disadvantages, however. The T1 vernier value and the period vernier value can compound the inaccuracies caused by the nonlinear analog nature of vernier circuits having a large span. Also, the linearity of the vernier circuits can vary between output pins, thereby increasing skew among the waveforms.
Moreover, the distribution of the period start signal typically requires a high bandwidth distribution tree because the tester period is typically programmable over a wide range. In addition, the distribution of the period vernier value from the central period generator to all of the marker generators typically increases the pin count of the automatic electrical test system components.
Past automatic electrical test systems that generate and distribute the period start signal from a central period generator cannot typically generate markers across multiple tester cycles boundaries unless multiple T1 counters are implemented in the marker generators. In such systems, a T1 counter is typically triggered on each cycle boundary in order to generate markers for the intervening cycles. If the multiple T1 counters are not implemented, marker generation across cycle boundaries would preclude on the fly changes in tester periods. Unfortunately, the multiple high speed T1 counters typically required by prior systems increase the cost and complexity of the automatic electrical test system hardware.